1. Technical Field
The present invention relates to an AD converter that converts an analog signal into a digital signal. In particular, the present invention relates to an AD converter that uses delta-sigma modulation.
2. Related Art
A circuit using delta-sigma modulation is known as an AD converter for converting an analog signal into a digital signal, as shown in, for example, Japanese Patent Application Publication No. 2001-24512. Delta-sigma modulation involves converting an analog signal into a digital signal by performing a feedback process to subtract a prescribed reference value from an added value when the value sequentially added to the level of the analog signal becomes greater than the reference value.
FIG. 10 shows a conventional AD converter 200. The AD converter 200 is provided with a level calculating section 210, an integrator 220, a 1-bit ADC 230, a signal processing section 240, a delay device 250, and a 1-bit DAC 260.
The integrator 220 integrates the level of the analog signal. The 1-bit ADC 230 outputs a binary signal indicating whether the output from the integrator 220 is greater than a reference value. The delay device 250 delays the signal output from the 1-bit ADC 230 by one cycle. Here, “one cycle” refers to one cycle of a sampling clock supplied to the 1-bit ADC 230. When supplied with a logic value of 1 from the delay device 250, the 1-bit DAC 260 outputs, to the level calculating section 210, a level corresponding to the reference value in the 1-bit ADC 230. The level calculating section 210 subtracts the level output by the 1-bit DAC 260 from the level of the input analog signal, and supplies the result to the integrator 220.
The signal processing section 240 generates a digital signal based on the signal output by the 1-bit ADC 230. For example, the signal processing section 240 may generate the digital signal according to the distribution of the timings at which the 1-bit ADC 230 outputs a logic value of 1.
As described above, the AD converter 200 generates the value of the digital signal based on the timing at which the 1-bit ADC 230 outputs a logic value of 1. Therefore, the AD converter 200 can generate the value of the digital signal with a higher resolution when the 1-bit ADC 230 has a higher sampling frequency and a higher resolution with respect to time.
However, there is a limit to how much the sampling frequency of the 1-bit ADC 230 can be enhanced simply by increasing the frequency of the sampling clock. Furthermore, it is difficult for the comparison result by the 1-bit ADC 230 to be fed back to the level calculating section 210 within a single cycle of a high-speed sampling clock.